CompE-470 Digital Circuits (with VHDL)

Summer 2004 Design Project

Objective

The objective of the design project is to apply the Digital Logic Design and VHDL knowledgebase developed during the course to design a real-world application or component.

You may choose whatever project you want, as long as you follow these ground rules:

· Your project is 15% of your final grade and should be worth it. That is, it has to encompass all combinatorial, sequential and FSM design in VHDL.

· It is strongly encouraged that you build your design in a hierarchy and simulate all sub-components individually so that you do not run into unexpected errors due to a weaker link.

· All real world design and hardware have delays and inertia in individual components. Your design must highlight and account for all such requirements and define clearly all design timing constraints.

· Your submitted design should be at least partially simulatable (i.e., should have signs of life) to receive a minimum passing grade in the project.

· A complete project should include timing level simulation, synthesis and device level place and route results in addition to the behavioral simulation.

· Remember that designs with a higher degree of difficulty may earn higher scores than those with a lower level of difficulty. Also, a design team project is expected to deliver more than an individual design project.

Project ideas

You may choose to do a design project on any idea that trickles your fantasy. However, some possible design project Ideas are listed (just for reference) below.

• Matrix Operations Unit
• Complex Arithmetic Logic Unit
• Multiplication, Division and Square root Computer
• A functional microprocessor design.
• Digital filter design: FIR/IIR filters, interpolating filter
• Generation of variable length Gold codes
• Programmable pulse generator (such as 8254)
• Encryption Algorithms
• Error detection and correction: Hamming Codes, Reed-solomon codes
• Networking: LAN/WAN switch
• Bus Arbiter for a real microprocessor
• Vending Machine Controller
• Multiple Elevator Management System
• Vehicle Parking Management system
• Washing Machine Controller
• Home Security Controller
• Exercise bike/treadmill mode and display controller
• Microwave Oven Controller
• Telephone Answering Machine
• Calculator

Project Report

Your project report binder should include the following

· Title page

· Table of Contents

· (5 points) Introduction

· (20 points) Description of the Project: This should include a textual explanation of the problem/design you are planning to do accompanied by your proposed solution, a block diagram, hardware justification/ requirements, FSM (or ASM) designs, any operational rule-base (fuzzy rules etc.), a master block diagram in case you are designing a component for a large project.

· (10 points) Explanation of various ports/signals/variables used in the design and a graphical block diagram showing their relationship.

· (30 points) Design: Your main report should have the following appendices

o Your VHDL code files

o a block diagram (or hierarchy) showing all your design entities/units (if applicable)

o Your test-bench/test-harness files. You can write VHDL testbenches or use the Xilinx testvector generation. Make sure that you generate a stimulus pattern that is both adequate and representative, i.e., it should capture the complete functionality of the design

o RTL level schematics

o Relevant excerpts from synthesized and/or implementation reports

· (25 points) Simulation Results: Behavioral and Timing Simulation Results. The simulated results should be commented to highlight various events

· (5 points) Observations, possible extensions and comments

· A single statement page by the design team explaining contributions of each team member

· (5 points) List of references: papers, websites and other references (be truthful)

** Your final design submission should be also accompanied by a CD containing all the design material (and any downloaded information that you used)

Note: (10 points) Writing competency will count towards your project grade. Pay attention to spelling, grammar, organization, and clarity. Number the pages of the report sequentially. Specify page numbers when referring to information that appears on another page. Proofread your report. Look up words in a dictionary or use a spelling checker. Consistently bad spelling is a source of embarrassment in intellectual circles, and cause for loss of points on this project.

The design specification and report must consist of at least five pages of double spaced 12 pt. text with none of the four margins larger than 3/4 of an inch. Furthermore, tricks like phony headings, paragraph titles and creative line skipping will not be tolerated.

Team Size & Deadlines

· Work teams may be 1-3 persons and must be established in the design specification. All constituted teams need to submit their final design specifications by June 21, 2004.

· Students should meet the instructor with their respective groups to discuss their project details before Jun 24, 2003

· The final report (either properly ring bound or punched and filed in a folder format) is due on July 1, 2004 in class.

· On the same day i.e., July 1, every group will be required to do a 5-7 minute concise presentation on the distinctive features of their project.

· The report should be accompanied by a CD/disk containing all the design data and other reference materials used for the project.

Minimum Performance Requirement

The following wo conditions must be satisfied for this project in order to avoid an failing grade for this course project:

1) The Modelsim^TM simulation must work to a certain extent, and a minimum score of 50 out of 100 points must be attained.

2) Reports that have an inadequate write-up will be returned for revision, however, the original report grade will be used in calculating the overall course grade.

Ethics

No two projects should look alike. If two projects look substantially similar, no credit will be given and both projects will be submitted to the student senate for review as an academic dishonesty incident.